The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2014

Filed:

Sep. 15, 2011
Applicants:

Jin Gu Kim, Gyunggi-do, KR;

MI Jin Park, Gyunggi-do, KR;

Young Ho Kim, Seoul, KR;

Seung Wook Park, Gyunggi-do, KR;

Hee Kon Lee, Gyunggi-do, KR;

Young DO Kweon, Seoul, KR;

Inventors:

Jin Gu Kim, Gyunggi-do, KR;

Mi Jin Park, Gyunggi-do, KR;

Young Ho Kim, Seoul, KR;

Seung Wook Park, Gyunggi-do, KR;

Hee Kon Lee, Gyunggi-do, KR;

Young Do Kweon, Seoul, KR;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/00 (2006.01); H05K 1/11 (2006.01); H05K 7/02 (2006.01); H01L 23/498 (2006.01); H05K 3/46 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4694 (2013.01); H01L 23/49822 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/15311 (2013.01); H05K 1/112 (2013.01); H05K 2203/041 (2013.01); H01L 23/49827 (2013.01); H01L 23/49816 (2013.01); H05K 3/3436 (2013.01);
Abstract

Disclosed herein is an interposer-embedded printed circuit board, including: a substrate including a cavity formed in one side thereof and having a predetermined height in a thickness direction of the substrate; an interposer disposed in the cavity and including a wiring region and an insulating region; and a circuit layer formed in the substrate and including a connection pattern connected with one side of the wiring region. The interposer-embedded printed circuit board is advantageous in that an interposer is embedded in a substrate, so that the thickness of a semiconductor package can be reduced, thereby keeping up with the trend of slimming the semiconductor package.


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