The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2014

Filed:

Sep. 26, 2009
Applicants:

Fransciscus Geradus Marie DE Jong, Valkenswaard, NL;

Alexander Sebastian Biewenga, Eindhoven, NL;

Inventors:
Assignee:

NXP, B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/02 (2006.01); G01R 31/26 (2014.01); G01R 31/3185 (2006.01); G01R 31/317 (2006.01); G01R 31/319 (2006.01); G01R 31/28 (2006.01); G01R 31/3183 (2006.01); G01R 19/00 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318555 (2013.01); G01R 31/31717 (2013.01); G01R 31/3185 (2013.01); G01R 31/31924 (2013.01); G01R 31/28 (2013.01); G01R 31/26 (2013.01); G01R 31/3183 (2013.01); G01R 19/00 (2013.01); G01R 31/318558 (2013.01);
Abstract

The present invention discloses a method of testing a partially assembled multi-die device () by providing a carrier () comprising a device-level test data input () and a device-level test data output (); placing a first die on the carrier, the first die having a test access port () comprising a primary test data input (), a secondary test data input () and a test data output (), the test access port being controlled by a test access port controller (); communicatively coupling the secondary test data input () of the first die to the device-level test data input (), and the test data output () of the first die to the device-level test data output (); providing the first die with configuration information to bring the first die in a state in which the first die accepts test instructions from its secondary test data input (); testing the first die, said testing including providing the secondary test data input () of the first die with test instructions through the device-level test data input (); and collecting a test result for the first die on the device-level test data output (). Consequently, a die of a partially assembled multi-die device such as a System-in-Package may be tested using its integrated boundary scan test architecture.


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Jong, Fransciscus Geradus Marie de. (2014). Method for testing a partially assembled multi-die device, integrated circuit die and multi-die device (U.S. Patent No. 8829940). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8829940

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