The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2014
Filed:
Nov. 06, 2012
Applicant:
Renesas Electronics Corporation, Kawasaki, JP;
Inventors:
Jun Kawahara, Kanagawa, JP;
Naoya Inoue, Kanagawa, JP;
Naoya Furutake, Kanagawa, JP;
Yoshihiro Hayashi, Kanagawa, JP;
Assignee:
Renesas Electronics Corporation, Kawasaki-shi, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2012.01); H01L 31/113 (2006.01); H01L 31/119 (2006.01); H01L 49/02 (2006.01); H01L 27/08 (2006.01); H01L 23/522 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 28/24 (2013.01); H01L 27/0802 (2013.01); H01L 23/5228 (2013.01); H01L 27/0629 (2013.01); Y10S 257/904 (2013.01);
Abstract
A semiconductor device includes a first insulating layer (interlayer insulating layer), a resistive element that is disposed over the first insulating layer (interlayer insulating layer) and at least a surface layer of which is a TaSiN layer, and an interlayer insulating layer disposed over the first insulating layer (interlayer insulating layer) and the resistive element. Multiple via plugs having ends coupled to the TaSiN layer are disposed in the interlayer insulating layer.