The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2014

Filed:

Nov. 17, 2010
Applicant:

Koray Oner, Cupertino, CA (US);

Inventor:

Koray Oner, Cupertino, CA (US);

Assignee:

Broadcom Corporation, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 13/16 (2006.01); G11C 29/02 (2006.01); G06F 11/27 (2006.01); G11C 29/56 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1673 (2013.01); G06F 11/27 (2013.01); G06F 2213/0038 (2013.01); G11C 29/02 (2013.01); G11C 2029/5602 (2013.01);
Abstract

The present application discloses a memory controller for accessing an external memory device. The memory controller comprises a bus interface and an internal memory buffer capable of accessing the bus interface. The internal memory buffer operates as an on-chip storage. In various embodiments of the disclosure, the internal memory buffer operates during a testing of a chip containing the memory controller. For example, the internal memory buffer may emulate the external memory device in response to an input signal. Moreover, in various embodiments of the disclosure, the external memory device may be a dynamic random access memory (DRAM), while the internal memory buffer may be a static random access memory (SRAM). The memory controller may be adapted to automated test equipment (ATE). Moreover, the memory controller may be incorporated onto a system-on-a-chip (SOC) along with one or more agents.


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