The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2014
Filed:
Dec. 16, 2008
Håkan Johansson, Linköping, SE;
Håkan Johansson, Linköping, SE;
Signal Processing Devices Sweden AB, Linkoping, SE;
Abstract
An estimation unit for estimating a nonlinearity error of a conversion circuit, such as an ADC, is adapted to receive a continuous-time input signal and output a digital output signal. In at least one embodiment, the continuous-time input signal is essentially bandlimited to an angular frequency band [ω, ω], where ω>(L−1)π/T, ω<Lπ/T, L is a positive integer, and T is a sample period of the conversion circuit. The estimation unit includes an input port for receiving a digital input signal having a first sample rate 1/T and an output port for outputting a digital estimated error signal also having the first sample rate. For each integer P_k in a set of integers, the estimation unit a first linear filter unit for generating a first signal s(n) as a linear function of the digital input signal, an interpolation unit for interpolating the first signal s(n) to generate a second signal s(m) having a second sample rate which is a factor L·R_k higher than the first sample rate, wherein L·R_k≧ω·T·P_k/π, a nonlinearity unit for generating a third signal s(m) as (s(m)), and a second linear filter unit for generating a component of the estimated error signal based on the third signal s(m), wherein the component has the first sample rate. Furthermore, the estimation unit includes an adder circuit for generating the estimated error signal as the sum of the components of the estimated error signal. Moreover, at least one embodiment is directed to a compensation circuit including the estimation unit, corresponding methods for estimating and compensating nonlinearity errors, a computer program product, a computer readable medium, and a hardware-description entity.