The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2014

Filed:

Dec. 11, 2012
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Hoon Choi, Icheon-si, KR;

Jin Hee Cho, Icheon-si, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/22 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G11C 7/1066 (2013.01);
Abstract

An output enable signal generation circuit includes an output enable reset signal generation unit configured to enable an output enable reset signal in response to an external clock signal, a DLL locking signal, and a reset signal, an output enable reset signal delay unit configured to delay the output enable reset signal and output the delayed output enable reset signal, a counter unit configured to output the count of the external clock signal as a value in response to the output enable reset signal and the delayed output enable reset signal, a read command delay unit configured to delay a read command and output the delayed read command, and an output enable signal output unit configured to shift the delayed read command in synchronization with a DLL clock signal and output an output enable signal, according to control of CL and the count value.


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