Display device having memory in pixels

Abstract

The present invention relates to a memory circuit integrated in each pixel of a display device includes a switching circuit and a memory unit. The switching circuit includes a first transistor having a gate configured to receive a switching control signal, a source and a drain electrically coupled to a liquid crystal capacitor of the pixel, and a second transistor having a gate configured to receive a switching control signal, a source electrically coupled to a storage capacitor of the pixel, and a drain electrically coupled to the liquid crystal capacitor. The memory unit is electrically coupled between the source of first transistor and the storage capacitor. The switching control signal is configured such that in the normal mode, the first transistor is turned off, while the second transistor is turned on, so that the storage capacitor is electrically coupled to the liquid crystal capacitor in parallel and the memory unit is bypassed, and in the still mode, the first transistor is turned on, while the second transistor is turned off, so that the storage capacitor controls the memory unit to supply a stored data to the liquid crystal capacitor.