The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2014
Filed:
Oct. 13, 2010
Shuji Tanaka, Sendai, JP;
Masayoshi Esashi, Sendai, JP;
Masanori Muroyama, Sendai, JP;
Sakae Matsuzaki, Sendai, JP;
Mitsutoshi Makihata, Sendai, JP;
Yutaka Nonomura, Nagoya, JP;
Motohiro Fujiyoshi, Seto, JP;
Takahiro Nakayama, Nagoya, JP;
Ui Yamaguchi, Toyota, JP;
Hitoshi Yamada, Aichi-gun, JP;
Shuji Tanaka, Sendai, JP;
Masayoshi Esashi, Sendai, JP;
Masanori Muroyama, Sendai, JP;
Sakae Matsuzaki, Sendai, JP;
Mitsutoshi Makihata, Sendai, JP;
Yutaka Nonomura, Nagoya, JP;
Motohiro Fujiyoshi, Seto, JP;
Takahiro Nakayama, Nagoya, JP;
Ui Yamaguchi, Toyota, JP;
Hitoshi Yamada, Aichi-gun, JP;
Tohoku University, Sendai-Shi, JP;
Kabushiki Kaisha Toyota Chuo Kenkyusho, Aichi-Gun, JP;
Toyota Jidosha Kabushiki Kaisha, Toyota-Shi, JP;
Abstract
Provided is a technique for packaging a sensor structure having a contact sensing surface and a signal processing LSI that processes a sensor signal. The sensor structure has the contact sensing surface and sensor electrodes. The signal processing integrated circuit is embedded in a semiconductor substrate. The sensor structure and the semiconductor substrate are bonded by a bonding layer, forming a sensor device as a single chip. The sensor electrodes and the integrated circuit are sealed inside the sensor device, and the sensor electrodes and external terminals of the integrated circuit are led out to the back surface of the semiconductor substrate through a side surface of the semiconductor substrate.