The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2014

Filed:

Apr. 16, 2012
Applicants:

Jun-sheng LI, Taichung, TW;

Kuo-chen Wu, Taichung, TW;

Wei-chih Wen, Taichung, TW;

Inventors:

Jun-Sheng Li, Taichung, TW;

Kuo-Chen Wu, Taichung, TW;

Wei-Chih Wen, Taichung, TW;

Assignee:

Huga Optotech Inc., Taichung, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 33/20 (2010.01); H01L 33/38 (2010.01); H01L 33/40 (2010.01);
U.S. Cl.
CPC ...
H01L 33/20 (2013.01); H01L 33/40 (2013.01); H01L 33/38 (2013.01);
Abstract

A semiconductor light-emitting structure is provided, which includes a first doped type semiconductor layer, a light-emitting layer, a second doped type semiconductor layer, a first electrical transmission layer and at least one first conductor. The light-emitting layer is disposed on the first doped type semiconductor layer and the second doped type semiconductor layer is disposed on the light-emitting layer. The first electrical transmission layer is disposed on the first doped type semiconductor layer, in which a first interface is formed between the first electrical transmission layer and the first doped type semiconductor layer. The first conductor is disposed on the first doped type semiconductor layer. The first electrical transmission layer connects the first conductor. A second interface is formed between each of the first conductor and the first doped type semiconductor layer, and the resistance of the second interface is less than the resistance of the first interface.


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