The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2014

Filed:

Aug. 23, 2010
Applicants:

Michiko Takei, Osaka, JP;

Tohru Okabe, Osaka, JP;

Tetsuya Aita, Osaka, JP;

Tsuyoshi Inoue, Osaka, JP;

Yoshiyuki Harumoto, Osaka, JP;

Takeshi Yaneda, Osaka, JP;

Inventors:

Michiko Takei, Osaka, JP;

Tohru Okabe, Osaka, JP;

Tetsuya Aita, Osaka, JP;

Tsuyoshi Inoue, Osaka, JP;

Yoshiyuki Harumoto, Osaka, JP;

Takeshi Yaneda, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/036 (2006.01); H01L 21/268 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 29/04 (2006.01);
U.S. Cl.
CPC ...
H01L 21/268 (2013.01); H01L 27/1229 (2013.01); H01L 29/66765 (2013.01); H01L 29/04 (2013.01); H01L 27/1285 (2013.01); H01L 29/78678 (2013.01);
Abstract

An object of this invention is to provide a semiconductor device in which TFTs with high mobility are arranged in both of display and peripheral circuit areas. A semiconductor device fabricating method according to the present invention includes the steps of: irradiating an amorphous silicon layer () with energy, thereby obtaining a microcrystalline silicon layer; and forming a doped semiconductor layer () on the amorphous silicon layer (). In the step of irradiating, the amorphous silicon layer () is irradiated with energy that has a first quantity, thereby forming a first microcrystalline silicon layer (A) including a channel layer for a first TFT (A), and is also irradiated with energy that has a second quantity, which is larger than the first quantity, thereby forming a second microcrystalline silicon layer (B) including a channel layer for a second TFT (B).


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