The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2014
Filed:
Aug. 09, 2011
James Mark Mcgillivary, Portland, OR (US);
James Mark McGillivary, Portland, OR (US);
Other;
Abstract
A guitar amplifier system is disclosed. Specific implementations for the guitar amplifier system may comprise an audio input for an audio signal, a preamplifier coupled to the audio input, a tone control element coupled to the preamplifier, a power amplifier coupled to the tone control element, and an audio output coupled to the power amplifier. In an implementation, the tone control may be configured to control at least one of sound equalization, compression distortion, chorus or reverb. In an implementation, at least one of the preamplifier and the power amplifier may comprise at least one distortion multiplier circuit. The distortion multiplier circuit may comprise an audio signal multiplier configured to amplify an audio signal and output an amplified audio signal. The distortion multiplier circuit may also comprise a first voltage clamping circuit between a Vhigh preset level and a reference node coupled to the field effect transistor drain, and a second voltage clamping circuit between the Vlow preset level and the reference node. The Vhigh preset level and Vlow preset level may be set at different distances from a center voltage to asymmetrically distort the audio signal through asymmetrically limiting gain of the audio signal above the preset level and when compared with below the preset level. The distortion multiplier circuit may also comprise a blocking element configured to block DC biases of the field effect transistor.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile