Memory access circuit and memory access system

Abstract

According to one embodiment, a memory access circuit includes a PLL, a phy-clock tree, first, second, and master DLLs, and first and second PDs. The PLL generates a PLL output locked to a reference frequency. The phy-clock tree delays the PLL output and generates a reference clock signal. The first DLL corrects a clock skew between reference and system clock signals, and generates a source of the system clock signal. The second DLL corrects a clock skew between reference clock and phy-clock signals, and generates a source of the phy-clock signal. The first and second PDs detect a phase difference, and generate first and second detection signals. The master DLL counts the reference clock signal and generates a delay correction signal. The first and second DLLs determine a correction direction and a correction amount based on first and second detection and delay correction signals, respectively.