Low latency bypass buffer

Abstract

Buffer circuitryis provided with shared buffer circuitrywhich stores, in order of reception time, data transaction requests received from one or more data transaction sources. The buffer circuitryoperates in either a bypass mode or a non-bypass mode. When operating in the bypass mode, any low latency data transaction requests stored within the shared buffer circuitry are selected in order for output in preference to data transaction requests that are not low latency data transaction requests. In the non-bypass mode, transactions (whether or not they are low latency transactions) are output from the shared buffer circuitryin accordance with the order in which they are received into the shared buffer circuitry. The switch between the bypass mode and the non-bypass mode is made in dependence upon comparison of a detected rate of output of low latency data transaction requests compared to a threshold value. If the rate exceeds the threshold value, then the switch is made to the non-bypass mode so that data transaction requests which are not low latency data transaction requests are permitted a fair share of the output bandwidth.