The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2014

Filed:

Aug. 01, 2013
Applicant:

Panasonic Corporation, Osaka, JP;

Inventor:

Kazuyuki Kouno, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 5/08 (2006.01); G11C 7/10 (2006.01); G11C 13/00 (2006.01); G11C 11/22 (2006.01);
U.S. Cl.
CPC ...
G11C 5/063 (2013.01); G11C 7/1096 (2013.01); G11C 2013/0088 (2013.01); G11C 13/0069 (2013.01); G11C 2013/0073 (2013.01); G11C 2213/79 (2013.01); G11C 13/0002 (2013.01); G11C 5/08 (2013.01); G11C 11/2275 (2013.01);
Abstract

Each of m word lines is connected to n memory cells in a corresponding one of rows of m×n memory cells. Each of n bit lines is connected to m memory cells in a corresponding one of columns of m×n memory cells, and each of n source lines is connected to m memory cells in a corresponding one of columns of m×n memory cells. N first switching elements switch connection states between a reference node and the n bit lines, and n second switching elements switch connection states between the reference node and the n source lines. N third switching elements switch connection states between the write driver and the n bit lines, and n fourth switching elements switch connection states between the write driver and the n source lines.


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