The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 2014
Filed:
Oct. 25, 2013
Applicant:
Fujitsu Semiconductor Limited, Kanagawa, JP;
Inventors:
Mitsuhiro Hirano, Akisima, JP;
Shuji Hamada, Kawasaki, JP;
Assignee:
Fujitsu Semiconductor Limited, Yokohama, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
An electric circuit includes a delayed clock generation circuit to which a first clock is supplied and which is configured to generate a first delayed clock and a second delayed clock, the first delayed clock being the first clock delayed by a first delay amount, and the second delayed clock being the first clock delayed by a second delay amount different from the first delay amount, an OR gate configured to receive the first clock, the first delayed clock, and the second delayed clock as inputs and to output a second clock, and a scan circuit to which the second clock is supplied.