Clock generation circuit and semiconductor apparatus including the same

Abstract

A clock generation circuit includes a delay line, a delay modeling block, a phase detection block, a multi-update signal generation block, and a delay line. The delay line delays an input clock and generates a delayed clock. The delay modeling block delays the delayed clock by a modeled delay value and generates a feedback clock. The phase detection block compares phases of the input clock and the feedback clock and generates phase information, and quantizes a phase difference between the input clock and the feedback clock and generates phase codes. The multi-update signal generation block generates a multi-update signal in response to the phase codes. The delay line control block changes a delay amount of the delay line in response to the multi-update signal and the phase information.