The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 2014
Filed:
Dec. 08, 2008
Applicants:
Peter J. Hopper, San Jose, CA (US);
William French, San Jose, CA (US);
Kyuwoon Hwang, Palo Alto, CA (US);
Inventors:
Peter J. Hopper, San Jose, CA (US);
William French, San Jose, CA (US);
Kyuwoon Hwang, Palo Alto, CA (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01);
U.S. Cl.
CPC ...
Abstract
In a SOI process, a high lateral voltage isolation structure is formed by providing at least two concentric dielectric filled trenches, removing the semiconductor material between the dielectric filled trenches and filling the resultant gap with dielectric material to define a single wide dielectric filled trench.
Quick Actions:
Hopper, Peter. (2014). Method of forming high lateral voltage isolation structure involving two separate trench fills (U.S. Patent No. 8815700). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8815700
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile