The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2014

Filed:

Dec. 07, 2011
Applicants:

Byoung-keon Park, Yongin, KR;

Jong-ryuk Park, Yongin, KR;

Tak-young Lee, Yongin, KR;

Jin-wook Seo, Yongin, KR;

Ki-yong Lee, Yongin, KR;

Inventors:

Byoung-Keon Park, Yongin, KR;

Jong-Ryuk Park, Yongin, KR;

Tak-Young Lee, Yongin, KR;

Jin-Wook Seo, Yongin, KR;

Ki-Yong Lee, Yongin, KR;

Assignee:

Samsung Display Co., Ltd., Giheung-Gu, Yongin, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 33/08 (2010.01); H01L 33/16 (2010.01); H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a TFT, including forming a buffer layer, an amorphous silicon layer, an insulating layer, and a first conductive layer on a substrate, forming a polycrystalline silicon layer by crystallizing the amorphous silicon layer, forming a semiconductor layer, a gate insulating layer, and a gate electrode that have a predetermined shape by simultaneously patterning the polycrystalline silicon layer, the insulating layer, and the first conductive layer, wherein the polycrystalline silicon layer is further etched to produce an undercut recessed a distance compared to sidewalls of the insulating layer and the first conductive layer, forming source and drain regions within the semiconductor layer by doping corresponding portions of the semiconductor layer, forming an interlayer insulating layer on the gate electrode, the interlayer insulating layer covering the gate insulating layer and forming source and drain electrodes that are electrically connected to source and drain regions respectively.


Find Patent Forward Citations

Park, Byoung-Keon. (2014). Method of manufacturing thin film transistor, thin film transistor manufactured using the method, method of manufacturing organic light-emitting display apparatus, and organic light-emitting display apparatus manufactured using the method (U.S. Patent No. 8815663). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8815663

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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