The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2014

Filed:

Apr. 30, 2013
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Avinash Rath, Bangalore, IN;

Sanjith Sleeba, Bangalore, IN;

Ashish Kumar, Banagalore, IN;

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G01R 31/28 (2006.01); G01R 27/28 (2006.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5022 (2013.01); G06F 17/5081 (2013.01); G06F 2217/12 (2013.01); G06F 2217/14 (2013.01); G06F 11/07 (2013.01); G01R 31/28 (2013.01); G01R 27/28 (2013.01);
Abstract

A method includes reading, through a processor of a computing device communicatively coupled to a memory, a design of an electronic circuit as part of verification thereof. The method also includes extracting, through the processor, a set of optimized instructions of a test algorithm involved in the verification such that the set of optimized instructions covers a maximum portion of logic functionalities associated with the design of the electronic circuit. Further, the method includes executing, through the processor, the test algorithm solely relevant to the optimized set of instructions to reduce a verification time of the design of the electronic circuit.


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