The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2014

Filed:

May. 05, 2010
Applicants:

Mark N. Fullerton, Austin, TX (US);

Sathish Kumar Radhakrishnan, Irvine, CA (US);

Brent Mulholland, Boulder, CO (US);

Ravi S. Setty, Santa Clara, CA (US);

Inventors:

Mark N. Fullerton, Austin, TX (US);

Sathish Kumar Radhakrishnan, Irvine, CA (US);

Brent Mulholland, Boulder, CO (US);

Ravi S. Setty, Santa Clara, CA (US);

Assignee:

Broadcom Corporation, Irvine, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 1/32 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1668 (2013.01); G06F 1/3203 (2013.01); G06F 1/3275 (2013.01); Y02B 60/1225 (2013.01);
Abstract

Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.


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