The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8812575 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 19, 2014

Filed:

Jul. 06, 2011
Applicants:

Ramy Raafat, Cairo, EG;

Amira Mohamed, Cairo, EG;

Hossam Ali Hassan Fahmy, Cairo, EG;

Yasmeen Farouk, Cairo, EG;

Mostafa Elkhouly, Cairo, EG;

Tarek Eldeeb, Cairo, EG;

Rodina Samy, Cairo, EG;

Inventors:

Ramy Raafat, Cairo, EG;

Amira Mohamed, Cairo, EG;

Hossam Ali Hassan Fahmy, Cairo, EG;

Yasmeen Farouk, Cairo, EG;

Mostafa Elkhouly, Cairo, EG;

Tarek Eldeeb, Cairo, EG;

Rodina Samy, Cairo, EG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/552 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system including: an input processing unit configured to: extract a significant and a bias exponent from the decimal floating-point radicand; and calculate a normalized significand; a square root unit configured to: calculate, using a FMA unit, a refined reciprocal square-root of the normalized significand; calculate an unrounded square-root of the normalized significand by multiplying the refined reciprocal square-root by the normalized significand; and generate a rounded square-root based on a first difference between the normalized significand and a square of the unrounded square-root; a master control unit operatively connected to the input processing hardware unit and the square-root hardware unit and configured to calculate an exponent for the unrounded square-root based on the number of leading zeros and a precision of the decimal floating-point radicand; and an output formulation unit configured to output a decimal floating-point square-root of the radicand based on the rounded square-root and the exponent.


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