The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2014

Filed:

Apr. 04, 2007
Applicants:

Chi Bun Chan, San Jose, CA (US);

Jonathan B. Ballagh, Boulder, CO (US);

Nabeel Shirazi, San Jose, CA (US);

Inventors:

Chi Bun Chan, San Jose, CA (US);

Jonathan B. Ballagh, Boulder, CO (US);

Nabeel Shirazi, San Jose, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2006.01); G06F 17/50 (2006.01); G06F 11/36 (2006.01); G06F 17/22 (2006.01); G06F 11/267 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5027 (2013.01); G06F 9/455 (2013.01); G06F 11/3652 (2013.01); G06F 17/22 (2013.01); G06F 2217/86 (2013.01); G06F 11/267 (2013.01); G06F 17/5009 (2013.01);
Abstract

Approaches for simulating an electronic system. In one approach, a software co-simulation platform is configured to produce a first time sequence of values of a plurality of input ports of a design block of the electronic system, consume a second time sequence of values of a plurality of output ports of the design block, and generate access transactions for transferring the first and second sequences of values. The software co-simulation platform generates a plurality of reconfiguration transactions for transferring reconfiguration data for the design block. A PLD is configured to implement a communication block and a control block. The communication block receives the reconfiguration and access transactions from the software co-simulation platform, and the control block reconfigures programmable logic and interconnect resources of the PLD in response to the reconfiguration transactions. The control block also controls the emulation of the design block in response to the access transactions.


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