The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 2014
Filed:
Sep. 14, 2012
Applicants:
Suresh Natarajan Rajan, San Jose, CA (US);
Michael John Sebastian Smith, Palo Alto, CA (US);
David T. Wang, Thousand Oaks, CA (US);
Inventors:
Suresh Natarajan Rajan, San Jose, CA (US);
Michael John Sebastian Smith, Palo Alto, CA (US);
David T. Wang, Thousand Oaks, CA (US);
Assignee:
Google Inc., Mountain View, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/24 (2006.01); G11C 5/02 (2006.01); G11C 11/4093 (2006.01); G11C 7/10 (2006.01); G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
G11C 7/00 (2013.01); G11C 5/02 (2013.01); G11C 11/4093 (2013.01); G11C 7/10 (2013.01);
Abstract
Large capacity memory systems are constructed using multiple groups of memory integrated circuits or chips. The memory system includes one or more interface circuits for interfacing between the multiple groups of memory integrated circuits and a memory controller. The interface circuit may detect and/or recover failed data using error-checking information stored in a memory integrated circuit.