The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2014

Filed:

Sep. 09, 2011
Applicants:

Sung-min Hwang, Seoul, KR;

Hansoo Kim, Suwon-si, KR;

Changseok Kang, Seongnam-si, KR;

Wonseok Cho, Suwon-si, KR;

Jae-joo Shim, Suwon-si, JP;

Inventors:

Sung-Min Hwang, Seoul, KR;

Hansoo Kim, Suwon-si, KR;

Changseok Kang, Seongnam-si, KR;

Wonseok Cho, Suwon-si, KR;

Jae-Joo Shim, Suwon-si, JP;

Assignee:

Samsung Electronics Co., Ltd, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 27/115 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
Abstract

Three dimensional semiconductor memory devices are provided. The three dimensional semiconductor memory device includes a first stacked structure and a second stacked structure sequentially stacked on a substrate. The first stacked structure includes first insulating patterns and first gate patterns which are alternately and repeatedly stacked on a substrate, and the second stacked structure includes second insulating patterns and second gate patterns which are alternately and repeatedly stacked on the first stacked structure. A plurality of first vertical active patterns penetrate the first stacked structure, and a plurality of second vertical active patterns penetrate the second stacked structure. The number of the first vertical active patterns is greater than the number of the second vertical active patterns.


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