The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 2014
Filed:
May. 27, 2010
Chih-wei Chuang, Albany, CA (US);
Connie Chang-hasnain, Palo Alto, CA (US);
Forrest Grant Sedgwick, Berkeley, CA (US);
Wai Son Ko, Menlo Park, CA (US);
Chih-Wei Chuang, Albany, CA (US);
Connie Chang-Hasnain, Palo Alto, CA (US);
Forrest Grant Sedgwick, Berkeley, CA (US);
Wai Son Ko, Menlo Park, CA (US);
The Regents of the University of California, Oakland, CA (US);
Abstract
The present disclosure provides a catalyst-free growth mode of defect-free Gallium Arsenide (GaAs)-based nanoneedles on silicon (Si) substrates with a complementary metal-oxide-semiconductor (CMOS)-compatible growth temperature of around 400° C. Each nanoneedle has a sharp 2 to 5 nanometer (nm) tip, a 600 nm wide base and a 4 micrometer (μm) length. Thus, the disclosed nanoneedles are substantially hexagonal needle-like crystal structures that assume a 6° to 9° tapered shape. The 600 nm wide base allows the typical micro-fabrication processes, such as optical lithography, to be applied. Therefore, nanoneedles are an ideal platform for the integration of optoelectronic devices on Si substrates. A nanoneedle avalanche photodiode (APD) grown on silicon is presented in this disclosure as a device application example. The APD attains a high current gain of 265 with only 8V bias.