The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 12, 2014
Filed:
Jul. 06, 2011
Amira Mohamed, Cairo, EG;
Ramy Raafat, Cairo, EG;
Hossam Ali Hassan Fahmy, Cairo, EG;
Tarek Eldeeb, Cairo, EG;
Yasmeen Farouk, Cairo, EG;
Rodina Samy, Cairo, EG;
Mostafa Elkhouly, Cairo, EG;
Amira Mohamed, Cairo, EG;
Ramy Raafat, Cairo, EG;
Hossam Ali Hassan Fahmy, Cairo, EG;
Tarek Eldeeb, Cairo, EG;
Yasmeen Farouk, Cairo, EG;
Rodina Samy, Cairo, EG;
Mostafa Elkhouly, Cairo, EG;
SilMinds, LLC, Egypt, Cairo, EG;
Abstract
A circuit for performing a floating-point fused-multiply-add (FMA) calculation of a×b±c. The circuit includes (i) a partial product generation module having (a) a multiples generator unit configured to generate multiples of a multiplicand has m digit binary coded decimal (BCD) format, (b) a recoding unit configured to generate n+1 signed digits (SD) sets from a sum vector and a carry vector of a multiplier, and (c) a multiples selection unit configured to generate partial product vectors from the multiples of the multiplicand based on the n+1 SD sets and the sign of FMA calculation, and (ii) a carry save adder (CSA) tree configured to add the partial product vectors and an addend to generate a result sum vector and a result carry vector in a m+n digit BCD format.