The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 12, 2014
Filed:
Jun. 06, 2011
Hyeong-seok Yu, Seoul, KR;
Dong-kwan Suh, Hwaseong, KR;
Suk-jin Kim, Seoul, KR;
San Kim, Seoul, KR;
Yong-surk Lee, Seoul, KR;
Hyeong-Seok Yu, Seoul, KR;
Dong-Kwan Suh, Hwaseong, KR;
Suk-Jin Kim, Seoul, KR;
San Kim, Seoul, KR;
Yong-Surk Lee, Seoul, KR;
Samsung Electronics Co., Ltd., Suwon-si, KR;
Industry-Academic Cooperation Foundation, Yonsei University, Seoul, KR;
Abstract
A fixed multiply-add (FMA) apparatus and method are provided. The FMA apparatus includes a partial product generator configured to generate a partial sum and a partial carry, a carry save adder configured to generate a partial sum having a first bit size and a partial carry having the first bit size by adding the partial sum and the partial carry to least significant bits (LSBs) of the mantissa of a third floating-point number, a carry select adder configured to generate a mantissa having a second bit size by adding the first bit-size partial sum and the first bit-size partial carry to most significant bits (MSBs) of the third floating-point number, and a selector configured to transmit the first bit-size partial sum and the first bit-size partial carry to the carry save adder or the carry select adder according to whether the mantissa of the third floating-point number is zero.