The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 12, 2014
Filed:
Jun. 21, 2011
Takahiro Ochiai, Chiba, JP;
Mitsuru Goto, Chiba, JP;
Hiroko Sehata, Sapporo, JP;
Hiroyuki Higashijima, Konosu, JP;
Takahiro Ochiai, Chiba, JP;
Mitsuru Goto, Chiba, JP;
Hiroko Sehata, Sapporo, JP;
Hiroyuki Higashijima, Konosu, JP;
Japan Display Inc., Tokyo, JP;
Panasonic Liquid Crystal Display Co., Ltd., Hyogo, JP;
Abstract
A plurality of cascaded unit register circuits which comprises a bidirectional shift register include main stages and dummy stages at the top before the main stages and dummy stages at the bottom after the main stages. A k-th stage outputs a pulse Pin synchronization with a clock signal with a reference point Nbeing at H level. The main stages include terminals NSF and NSB for setting Nto H to which Pand Pare input, respectively, and terminals NRB and NRF for setting Nto L level to which Pand Pare input, respectively. The order of generation of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched. Top dummy stages do not have NRB. Bottom dummy stages do not have NRF.