The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2014

Filed:

Jan. 30, 2013
Applicants:

Anand Kumar Sinha, Noida, IN;

Sanjay K. Wadhwa, Noida, IN;

Inventors:

Anand Kumar Sinha, Noida, IN;

Sanjay K. Wadhwa, Noida, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/26 (2006.01); H03K 3/36 (2006.01);
U.S. Cl.
CPC ...
H03K 3/36 (2013.01);
Abstract

A relaxation oscillator for generating an output clock signal includes an RC circuit, a self-biased comparator stage, and a logic circuit. The RC circuit generates first and second comparator input signals that are provided to the self-biased comparator stage. The self-biased comparator stage includes first and second input stages and a voltage reference circuit. Each of the first and second input stages in conjunction with the voltage reference circuit forms a comparator, i.e., first and second comparators corresponding to the first and second input stages, respectively. The self-biased comparator stage generates first and second comparator output signals, based on the first and second comparator input signals. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal.


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