The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 12, 2014
Filed:
Nov. 06, 2013
Amit Roy, Noida, IN;
Amit Kumar Dey, Noida, IN;
Kulbhushan Misri, Gurgaon, IN;
Vijay Tayal, Noida, IN;
Chetan Verma, Noida, IN;
Amit Roy, Noida, IN;
Amit Kumar Dey, Noida, IN;
Kulbhushan Misri, Gurgaon, IN;
Vijay Tayal, Noida, IN;
Chetan Verma, Noida, IN;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
Forward bulk biasing circuitry for PMOS and NMOS transistors is provided. The bulk biasing circuitry includes two N-type MOS transistors, two P-type MOS transistors, and two capacitors. The forward bias to a bulk terminal of a transistor increases a threshold voltage of a transistor, thereby reducing a transition time and improving the performance of the transistor. The forward bias is provided only when the transistor transitions from one state to another, thereby reducing leakage power dissipation during active and standby modes of an integrated circuit that includes the transistor.