The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2014

Filed:

Aug. 12, 2011
Applicants:

Tailiang Guo, Fujian, CN;

Yun YE, Fujian, CN;

Zhixian Lin, Fujian, CN;

Yongai Zhang, Fujian, CN;

Liqin Jiu, Fujian, CN;

Yuxiang You, Fujian, CN;

Inventors:

Tailiang Guo, Fujian, CN;

Yun Ye, Fujian, CN;

Zhixian Lin, Fujian, CN;

Yongai Zhang, Fujian, CN;

Liqin Jiu, Fujian, CN;

Yuxiang You, Fujian, CN;

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01J 1/62 (2006.01); H01J 63/04 (2006.01); H01J 29/08 (2006.01); H01J 31/12 (2006.01);
U.S. Cl.
CPC ...
H01J 63/04 (2013.01); H01J 29/08 (2013.01); H01J 2329/4608 (2013.01); H01J 2329/4669 (2013.01); H01J 2329/4682 (2013.01); H01J 31/127 (2013.01);
Abstract

The present invention relates to a symmetric quadrupole structured field emission display without spacer comprising the upper and under substrates with a dielectric layer in between, wherein comb-like dielectric layer with lateral connection belts and a number of longitudinal working belts and longitudinal anodes are arranged on the upper substrate, bus electrodes are arranged longitudinally along the center on each anode, on the top, longitudinal alternating phosphor layer and dielectric layer for isolation on anode, gate electrodes are arranged on both sides of each longitudinal work belts, with the bus electrode as symmetry center, forming interdigital gate electrodes, horizontal cathode electrodes and longitudinal auxiliary electrodes are on the under substrate, resistor layer for current limiting and dielectric layer for cathode protection are arranged alternating horizontally on each cathode electrode, each intersect of the auxiliary electrode and cathode is isolated by the dielectric layer for cathode.


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