The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2014

Filed:

Aug. 26, 2011
Applicants:

Ki-taeg Shin, Gyeongsangbuk-do, KR;

Sung-jin Kim, Daegu, KR;

Inventors:

Ki-Taeg Shin, Gyeongsangbuk-do, KR;

Sung-Jin Kim, Daegu, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 33/08 (2010.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1214 (2013.01);
Abstract

A method of manufacturing an array substrate for an FFS mode LCD device includes forming a gate line and a gate electrode on a substrate, forming a pixel electrode in the pixel region, forming a gate insulating layer on the gate line, the gate electrode and the pixel electrode, forming a data line, a source electrode, a drain electrode, and a semiconductor layer on the gate insulating layer, forming a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer including a drain contact hole and a pixel contact hole, and forming a connection pattern and a common electrode on the passivation layer, wherein the common electrode includes bar-shaped first openings in the pixel region, and the connection pattern contacts the drain electrode and the pixel electrode through the drain contact hole and the pixel contact hole, respectively.


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