The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2014

Filed:

Oct. 17, 2011
Applicants:

Wenwu Wang, Beijing, CN;

Chao Zhao, Kessel-Lo, BE;

Kai Han, Beijing, CN;

Dapeng Chen, Beijing, CN;

Inventors:

Wenwu Wang, Beijing, CN;

Chao Zhao, Kessel-Lo, BE;

Kai Han, Beijing, CN;

Dapeng Chen, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 21/8234 (2006.01); H01L 29/51 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82345 (2013.01); H01L 21/823842 (2013.01); H01L 21/28114 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 21/823468 (2013.01); H01L 21/823828 (2013.01); H01L 29/513 (2013.01); H01L 29/6653 (2013.01); H01L 21/823864 (2013.01); H01L 29/42376 (2013.01);
Abstract

A semiconductor device and a method for manufacturing the same, the method comprising: providing a semiconductor substrate; forming a dummy gate area on the substrate, forming spacers on sidewalls of the gate area, and forming source and drain areas in the semiconductor substrate on both sides of the dummy gate area, the dummy gate area comprising an interface layer and a dummy gate electrode; forming a dielectric cap layer on the dummy gate area and source and drain areas; planarizing the device with the dielectric cap layer on the source and drain areas as a stop layer; further removing the dummy gate electrode to expose the interface layer; and forming replacement gate area on the interface layer. The thickness of the gate groove may be controlled by the thickness of the dielectric cap layer, and the replacement gates of desired thickness and width may be further formed upon requirements. Thus, the aspect ratio of the gate groove is reduced and a sufficient low gate resistance is ensured.


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