The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2014
Filed:
Jan. 28, 2011
Minsik Cho, Cedar Park, TX (US);
Xiaoping Tang, Mohegan Lake, NY (US);
Minsik Cho, Cedar Park, TX (US);
Xiaoping Tang, Mohegan Lake, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An initial layout of at least a portion of a given layer of an integrated circuit design is decomposed into multiple sub-layouts by splitting each of a plurality of shapes of the initial layout into multiple segments, constructing a constraint graph to represent relationships between the segments, reducing the constraint graph to a stitch graph, determining at least one cut line of the stitch graph, and generating a decomposed layout based on the determined cut line. The decomposed layout in an illustrative embodiment includes first and second sub-layouts comprising respective disjoint subsets of the segments, with each of the sub-layouts of the decomposed layout being associated with a different pattern mask of a double patterning lithography process. The layout decomposition process advantageously minimizes the number of stitches between the sub-layouts without introducing excessive computational complexity.