The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2014

Filed:

Mar. 31, 2011
Applicants:

Xiping Zhou, Shenzhen, CN;

Jingyu LI, Shenzhen, CN;

Inventors:

Xiping Zhou, Shenzhen, CN;

Jingyu Li, Shenzhen, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/12 (2006.01); G06F 12/08 (2006.01); G06F 15/167 (2006.01); G06F 13/38 (2006.01);
U.S. Cl.
CPC ...
G06F 13/38 (2013.01); G06F 12/0815 (2013.01); G06F 12/08 (2013.01); G06F 12/0811 (2013.01); G06F 15/167 (2013.01); G06F 12/084 (2013.01);
Abstract

A method and an apparatus for implementing multi-processor memory coherency are disclosed. The method includes: a Level-2 (L2) cache of a first cluster receives a control signal of the first cluster for reading first data; the L2 cache of the first cluster reads the first data in a Level-1 (L1) cache of a second cluster through an Accelerator Coherency Port (ACP) of the L1 cache of the second cluster if the first data is currently maintained by the second cluster, where the L2 cache of the first cluster is connected to the ACP of the L1 cache of the second cluster; and the L2 cache of the first cluster provides the first data read to the first cluster for processing. The technical solution under the present invention implements memory coherency between clusters in the ARM Cortex-A9 architecture.


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