The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2014

Filed:

Oct. 11, 2012
Applicant:

Hitachi, Ltd., Tokyo, JP;

Inventors:

Yuki Sakashita, Yokohama, JP;

Yusuke Nonaka, Sagamihara, JP;

Shintaro Kudo, Yokohama, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 12/08 (2006.01); G06F 12/12 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0862 (2013.01); G06F 12/126 (2013.01); G06F 12/0888 (2013.01);
Abstract

To raise the CPU cache hit rate and improve the I/O processing. Controller is CPU configured from a CPU core and a CPU cache wherein the CPU selects memory bus optimization execution processing or cache poisoning optimization execution processing according to an attribute of the access target volume on the basis of an access request. If the memory bus optimization execution processing is selected, CPU loads the target data into the CPU core after storing the target data in the main storage area, and if the cache poisoning optimization execution processing is selected, the CPU loads the target data into the CPU core after storing the target data in the temporary area of the CPU cache from the CPU memory, and the CPU core checks the target data which was loaded from the main storage area or the temporary area of the CPU cache.


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