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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8798386 B1

PDFFull Text
Date of Patent:
Aug. 05, 2014

Filed:

Jul. 13, 2010

Method and system for processing image data on a per tile basis in an image sensor pipeline

Applicants:

Adrian Lees, Bar Hill, GB;

David Plowman, Great Chesterford, GB;

Inventors:

Adrian Lees, Bar Hill, GB;

David Plowman, Great Chesterford, GB;

Assignee:

Broadcom Corporation, Irvine, CA (US);

Attorney:

Brinks Gilson & Lione

Primary Examiner:

Randolph I Chu

Assistant Examiner:

Nathan Bloom

Int. Cl.
CPC ...
G06K 9/40 (2006.01); G06K 9/20 (2006.01); G06K 9/60 (2006.01); G06F 13/14 (2006.01); G06F 15/00 (2006.01); G06F 15/76 (2006.01); G06F 7/38 (2006.01); G06F 15/78 (2006.01); G06F 9/38 (2006.01); G06F 9/44 (2006.01); G06T 1/20 (2006.01); G06F 9/445 (2006.01);
U.S. Cl.
CPC ...
G06F 15/7885 (2013.01); G06F 9/3867 (2013.01); G06F 2212/17 (2013.01); G06F 2212/171 (2013.01); G06F 2009/44531 (2013.01); G06F 9/4405 (2013.01); G06T 1/20 (2013.01); G06T 2207/10004 (2013.01); G06T 2207/20021 (2013.01); G06T 2210/52 (2013.01);
Abstract

Methods and systems for processing image data on a per tile basis in an image sensor pipeline (ISP) are disclosed and may include communicating, to one or more processing modules via control logic circuits integrated in the ISP, corresponding configuration parameters that are associated with each of a plurality of data tiles comprising an image. The ISP may be integrated in a video processing core. The plurality of data tiles may vary in size. A processing complete signal may be communicated to the control logic circuits when the processing of each of the data tiles is complete prior to configuring a subsequent processing module. The processing may comprise one or more of: lens shading correction, statistics, distortion correction, demosaicing, denoising, defective pixel correction, color correction, and resizing. Each of the data tiles may overlap with adjacent data tiles, and at least a portion of them may be processed concurrently.

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