The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8798226 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 05, 2014

Filed:

Feb. 06, 2013
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Sho Nagao, Tochigi, JP;

Yoshifumi Tanada, Kanagawa, JP;

Yutaka Shionoiri, Kanagawa, JP;

Hiroyuki Miyake, Kanagawa, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTsandto turn ON the TFTs and a potential of a node α is raised. When the potential of the node α reaches (VDD−VthN), the node α becomes in a floating state. Accordingly, a TFTis turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential of a gate electrode of the TFTis further raised due to an operation of a capacitance meansas the potential of the output node is raised, so that the potential of the gate electrode of the TFTbecomes higher than (VDD+VthN). Thus, the potential of the output node is raised to VDD without causing a voltage drop due to a threshold voltage of the TFT. An output at the subsequent stage is then inputted to a TFTto turn the TFTON, while the potential of the node α of TFTsandis dropped to turn the TFTOFF. As a result, the potential of the output node becomes Low level.


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