The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2014
Filed:
Jul. 04, 2012
Qi-long Yu, Guangdong, CN;
Tsung-jen Chuang, New Taipei, TW;
Jun Zhang, Guangdong, CN;
Jun-wei Zhang, Guangdong, CN;
Qi-Long Yu, Guangdong, CN;
Tsung-Jen Chuang, New Taipei, TW;
Jun Zhang, Guangdong, CN;
Jun-Wei Zhang, Guangdong, CN;
Fu Tai Hua Industry (Shenzhen) Co., Ltd., Shenzhen, CN;
Hon Hai Precision Industry Co., Ltd., New Taipei, TW;
Abstract
An electronic load for testing stability of a power voltage of a power source under test (PSUT) includes a voltage supply device, a field effect transistor (FET), an amplification circuit, and a current sampling resistor. The amplification circuit includes a first input, a second input, and an output. The voltage supply device is connected to the first input. The second input is connected to a source electrode of the FET. The output is connected to a gate electrode of the FET. A drain electrode of the FET is connected to the PSUT. One end of the current sampling resistor is grounded, and the other end of the current sampling resistor is connected to the source electrode of the FET and the second input. The voltage supply device outputs a control voltage. The amplification circuit amplifies the control voltage and drives the FET using the amplified control voltage.