The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8797077 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 05, 2014

Filed:

Jun. 19, 2013
Applicant:

Fujitsu Limited, Kawasaki, JP;

Inventor:

Ryuhei Sasagawa, Koto, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/289 (2006.01);
U.S. Cl.
CPC ...
Abstract

A master-slave flip-flop circuit includes: a master circuit to receive input data in a first state of a reference clock and hold the input data in a second state of the reference clock to output intermediary data; and a slave circuit to receive the intermediary data in the second state and hold the intermediary data in the first state to output data, wherein the master circuit includes: a feedback two-input NOR gate to receive an output of the master circuit and a first clock; an input three-input NOR gate to receive the input data, a second clock, and a third clock; and a synthesis two-input NOR gate to receive an output of the input three-input NOR gate and an output of the feedback two-input NOR gate.


Find Patent Forward Citations

Sasagawa, Ryuhei. (2014). Master-slave flip-flop circuit (U.S. Patent No. 8797077). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8797077

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