The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2014
Filed:
Aug. 03, 2011
Applicants:
Hongmei Liao, San Diego, CA (US);
Riko Radojcic, San Diego, CA (US);
Inventors:
Hongmei Liao, San Diego, CA (US);
Riko Radojcic, San Diego, CA (US);
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
Timing, power and SPICE analysis are performed on a circuit layout, based on temperature and stress variations or gradient across the circuit layout. Specifically, the temperature and stress values of individual window locations across the layout are used to obtain temperature and stress variation aware resistance/capacitance (RC), timing, leakage and power values. In addition, in 3D integrated circuits (IC), the stress and thermal variations or gradients of one die may be imported to another die located on a different tier.