The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2014

Filed:

May. 15, 2012
Applicants:

Kurt Ulmer, Vancouver, WA (US);

Kanan Puntambekar, Portland, OR (US);

Inventors:

Kurt Ulmer, Vancouver, WA (US);

Kanan Puntambekar, Portland, OR (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 51/00 (2006.01); H01L 21/288 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 51/0022 (2013.01); H01L 21/288 (2013.01); H01L 29/41733 (2013.01);
Abstract

A method is provided for controlling the channel length in a thin-film transistor (TFT). The method forms a printed ink first source/drain (S/D) structure overlying a substrate. A fluoropolymer mask is deposited to cover the first S/D structure. A boundary region is formed between the edge of the fluoropolymer mask and the edge of the printed ink first S/D structure, having a width. Then, a primary ink is printed at least partially overlying the boundary region, forming a printed ink second S/D structure, having an edge adjacent to the fluoropolymer mask edge. After removing the fluoropolymer mask, the printed ink first S/D structure edge is left separated from the printed ink second S/D structure edge by a space equal to the boundary region width. A semiconductor channel is formed partially overlying the first and second S/D structures, having a channel length equal to the boundary region width.


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