The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 29, 2014
Filed:
May. 27, 2013
Amit Roy, Greater Noida, IN;
Shyam S. Gupta, Nodia, IN;
Nipun Mahajan, New Delhi, IN;
Vijay Tayal, Nodia, IN;
Chetan Verma, Nodia, IN;
Amit Roy, Greater Noida, IN;
Shyam S. Gupta, Nodia, IN;
Nipun Mahajan, New Delhi, IN;
Vijay Tayal, Nodia, IN;
Chetan Verma, Nodia, IN;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A system and method for determining power leakage of an electronic circuit design that includes a plurality of digital logic elements, using an electronic design automation (EDA) tool that includes a processor and an automatic test pattern generation (ATPG) tool for generating multiple sets of input value strings. The ATPG tool generates test patterns that include input value strings for simulating each digital logic element of the circuit design independently. A mapping between generated output values and corresponding input values is stored in a look up table (LUT). Thereafter, the ATPG tool generates test patterns that include input value strings for simulating the real-time behavior of the circuit design. The processor determines power leakage of the circuit design based on probability of occurrence of each unique input value string at the input of each digital logic element and corresponding predetermined power leakage values.