The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8792835 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 29, 2014

Filed:

Sep. 22, 2009
Applicants:

David Andreu, Montarnaud, FR;

Philippe Cauvet, Caen, FR;

Marie-lise Flottes, St Georges d'orques, FR;

Ziad Noun, Baalbeck, LB;

Serge Bernard, St Georges d'orques, FR;

Inventors:

David Andreu, Montarnaud, FR;

Philippe Cauvet, Caen, FR;

Marie-Lise Flottes, St Georges d'orques, FR;

Ziad Noun, Baalbeck, LB;

Serge Bernard, St Georges d'orques, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 17/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and method for wirelessly testing integrated circuits provides a multiple layer interface to wirelessly test integrated circuits. A wireless testing structure for an integrated circuit comprises a wireless transceiver and a wireless test interface. The wireless transceiver is configured to receive test information from a tester and transmit test result information to the tester. The wireless test interface is configured to interface between the wireless transceiver and the integrated circuit. The wireless test interface comprises a media access controller and a test control block. The media access controller is configured to implement a media access control protocol for wireless communication. The test control block is configured to decode test information received from the tester, to trigger a test of the integrated circuit in response to the decoded test information, and to encode test result information that is generated by the integrated circuit in response to the test.


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