The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 29, 2014
Filed:
Feb. 27, 2012
Germano Nicollini, Piacenza, IT;
Carlo Pinna, Milan, IT;
Germano Nicollini, Piacenza, IT;
Carlo Pinna, Milan, IT;
ST-Ericsson SA, Plan-les-Quates, CH;
Abstract
The invention relates to a two stage class AB operational amplifier for driving a load, comprising at least an input stage comprising differential input terminals and an output terminal to provide a driving signal. In addition, the operational amplifier comprises an output stage comprising a first and second input terminals operatively associated to the input stage to be driven on the basis of said driving signal and a driving circuit operatively interposed between said input stage and the output stage. The operational amplifier is characterized in that the driving circuit comprises a first portion comprising at least one resistor operatively connected between a first reference potential via a first circuitry block comprising a PMOS transistor and a second reference potential via a second circuitry block comprising a NMOS transistor. The voltage drop on said at least a first resistor is fixed to a value depending on said first and second reference potentials and the gate-source voltages of said PMOS and NMOS transistors, respectively. The driving circuit further comprises a second portion comprising a first resistor and a second resistor having first terminals connected one another in a common terminal which is connected to the output terminal of the input stage. Said first resistor has a second terminal connected the first input terminal of the output stage and said second resistor has a second terminal connected to the second input terminal of the output stage. Said second terminals of the first and second resistors (R') are connected to the first reference potential via a third circuitry block and to the second reference potential (GND) via a fourth circuitry block, respectively. Said third (MW, M) and fourth (M, MX) circuitry blocks are arranged to be operatively connected to said first and second circuitry blocks, respectively, so that the voltage drop between the second terminals is substantially equal to the value of the voltage drop (VR) across said at least one resistor.