The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 29, 2014
Filed:
Aug. 31, 2012
Hui Liu, Pleasanton, CA (US);
Christopher F. Lane, San Jose, CA (US);
Arifur Rahman, San Jose, CA (US);
Jianming Huang, San Jose, CA (US);
Hui Liu, Pleasanton, CA (US);
Christopher F. Lane, San Jose, CA (US);
Arifur Rahman, San Jose, CA (US);
Jianming Huang, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Techniques and mechanisms for providing embedded Input/Output (IO) blocks in a floor plan of a semiconductor device are provided, where the embedded IO blocks constitute partial columns (i.e., they do not extend from the bottom through to the top of the semiconductor device). In some embodiments, the partial column IO banks are skewed away from one another. In some embodiments, the partial column IO banks are located away from the center of the semiconductor device. Techniques and mechanisms for implementing symmetrical package routing using skewed partial column IO banks are also provided.