The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2014

Filed:

Aug. 20, 2013
Applicant:

Baysand Inc., Morgan Hill, CA (US);

Inventors:

Jonathan C Park, San Jose, CA (US);

Salah M Werfelli, Morgan Hill, CA (US);

WeiZhi Kang, Kelantan, MY;

Wan Tat Hooi, Perak, MY;

Kok Siong Tee, Penang, MY;

Jeremy Jia Jian Lee, Perak, MY;

Assignee:

Baysand Inc., Morgan Hill, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit includes a gate array layer having a two-dimensional array of logic gates, each logic gate including multiple transistors. At least one upper template-based metal layer is coupled to the gate array layer and is configured to define at least one of a power distribution network, a clock network and a global signal network. A configuration of traces of the upper template-based metal layer is at least mainly predetermined prior to design of the integrated circuit.


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