The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2014

Filed:

Aug. 13, 2009
Applicants:

Mathias Kohlenz, San Diego, CA (US);

Idreas Mir, San Diego, CA (US);

Irfan Anwar Khan, Brooklyn, NY (US);

Sathyanarayan Madhusudan, San Diego, CA (US);

Shailesh Maheshwari, San Diego, CA (US);

Srividhya Krishnamoorthy, San Diego, CA (US);

Sandeep Urgaonkar, San Diego, CA (US);

Thomas Klingenbrunn, San Diego, CA (US);

Tim Liou, Taipei, TW;

Inventors:

Mathias Kohlenz, San Diego, CA (US);

Idreas Mir, San Diego, CA (US);

Irfan Anwar Khan, Brooklyn, NY (US);

Sathyanarayan Madhusudan, San Diego, CA (US);

Shailesh Maheshwari, San Diego, CA (US);

Srividhya Krishnamoorthy, San Diego, CA (US);

Sandeep Urgaonkar, San Diego, CA (US);

Thomas Klingenbrunn, San Diego, CA (US);

Tim Liou, Taipei, TW;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 9/5016 (2013.01);
Abstract

Multiple memory pools are defined in hardware for operating on data. At least one memory pool has a lower latency that the other memory pools. Hardware components operate directly on data in the lower latency memory pool.


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