The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2014

Filed:

Dec. 03, 2012
Applicant:

Spansion Llc, Sunnyvale, CA (US);

Inventors:

Masaru Yano, Tokyo, JP;

Kazuhide Kurosaki, Tokyo, JP;

Mototada Sakashita, Tokyo, JP;

Assignee:

Spansion LLC, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 5/06 (2006.01); G11C 7/00 (2006.01); G11C 5/02 (2006.01); G11C 16/24 (2006.01); G11C 7/18 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0491 (2013.01); G11C 16/0483 (2013.01); G11C 16/0408 (2013.01); G11C 16/24 (2013.01); G11C 5/02 (2013.01); G11C 5/06 (2013.01); G11C 7/18 (2013.01);
Abstract

An embodiment of the invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. One embodiment of the invention also provides a method of controlling the semiconductor device.


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