Delay circuits for simulating delays based on a single cycle of a clock signal

Abstract

In an embodiment, a delay circuit includes a ring oscillator circuit and a counter circuit. The ring oscillator circuit includes a delay chain having delay elements and configured to generate one of more clock cycles of an oscillator clock signal in response to a clock cycle of a clock signal. The counter circuit includes two counters that are configured to store a count state corresponding to a number of clock cycles of the oscillator clock signal during a single clock cycle of the clock signal. A first buffer is configured to store the number of clock cycles of the oscillator clock signal. The delay circuit includes a buffer to store a bit pattern corresponding to a number of delay elements traversed in a partial clock cycle of the oscillator clock signal in response to the clock cycle of the clock signal based on outputs of the plurality of delay elements.